The present invention relates to data processing technology, and more specifically to technology that can be effectively adapted to identifying processors in a system to which a plurality of processors are coupled, such as a system for designating coprocessors in a microcomputer system that has a plurality of coprocessors of the same kind.
In a microprocessor having high functions such as of 16 bits or 32 bits, a system is often constituted by coupling coprocessors such as FPU's (floating point units) in order to carry out numerical operations at high speeds. In addition to the above FPU's, the coprocessors are designed in a variety of other ways depending upon the applications and must be used selectively to meet the objects. Further, it may often be desired to operate coprocessors of the same kind in parallel or in a multiplexed manner. Therefore, a system having a plurality of coprocessors requires a method of identifying the coprocessors.
According to a conventional method of identifying the coprocessors in a system that has coprocessors, a coprocessor identification field is provided in an instruction word of the microprocessor, and a code of the identification field is sent onto an address bus at the time of executing the coprocessor instruction. Then, the coprocessor identification code is decoded by, for example, an external decoder to form a chip select signal which activates the designated coprocessor (see Japanese Patent Laid-Open No. 201154/1984).
In the above coprocessor identification system where the microprocessor instruction contains a coprocessor identification field, extension of the processor instruction set is limited by the width of the identification field. The conventional coprocessor identification system requires an external circuit to decode the identification field. Moreover, the conventional coprocessor identification system is limited to applications where the identification code of the coprocessor is fixed. Further, when a system using a plurality of coprocessors of the same type are operated in a multiplexed manner, it is not possible to distinguish one coprocessor from the other coprocessors with a single instruction. To make such a distinction, therefore, it is necessary to carry out the decoding operation which is quite different from the above-mentioned operation. Therefore, the instruction word must be furnished with data (code) that helps identify that the instruction is a coprocessor instruction even though it is apparent that the instruction is a coprocessor instruction.